PCB Laminated Reference

1.1 single deck and double sided panels;

For the two laminates, there is no stacking problem because of the small number of laminates. The control of EMI radiation mainly depends on the wiring and layout. The electromagnetic compatibility of single and double plate is more and more prominent. The main reason for this phenomenon is that the signal circuit area is too large, not only produce a strong electromagnetic radiation, but also make the circuit sensitive to external interference. The easiest way to improve the electromagnetic compatibility of a line is to reduce the loop area of the key signal.

Key signal: from the point of view of electromagnetic compatibility, the key signal mainly refers to the signal which produces strong radiation and the sensitive signal of the outside world. A signal that produces a strong radiation, usually a periodic signal, such as a low bit of a clock or address. Signals that are sensitive to interference refer to analog signals with lower levels.

Single and double deck plates are normally used in low frequency analog designs below 10KHz:

1 the power lines in the same layer radiate radially, and minimize the total length of the line;

2, when the power supply and ground wire, close to each other; in the key signal line cloth on the ground line, the ground line should be as close as possible to the signal line. Thus, smaller loop area is formed to reduce the sensitivity of differential mode radiation to external interference. When the signal line alongside a ground after the formation of a minimum area of the circuit, the signal current will take the loop, rather than the other wire path.

3, if it is a double circuit board, you can spread a ground wire along the signal line on the other side of the circuit board, next to the nearest signal line, and make the line as wide as possible. The loop area thus formed is equal to the thickness of the circuit board multiplied by the length of the signal line.

1.2, four ply laminates;

Laminate mode:

1.2.1 SIGGND (PWR) PWR (GND) SIG;

1.2.2 GNDSIG (PWR) SIG (PWR) GND;

For the above two kinds of stacked designs, the potential problem is the thickness of the conventional 1.6mm (62mil) plate. The spacing between layers will be very large, not only for controlling impedance, interlayer coupling and shielding, but also for greatly reducing the capacitance between the layers of power supply and reducing the noise.

For the first scenario, it is usually applied to more chips on the board. This scheme gives better SI performance and is not very good for EMI performance, mainly by routing and other details. Main attention: the stratum is placed on the connecting layer of the most dense signal layer, which is beneficial for absorbing and restraining radiation, increasing the plate area and reflecting the 20H rule.

For the second scheme, it is usually applied to the case where the chip density is low enough and sufficient area around the chip (placing the required power to cover the copper layer). In this scheme, the outer layer of PCB is stratum, and the middle two layers are signal / power layer. The power supply on the signal layer travels with a wide line, which makes the path impedance of the supply current low, and the impedance of the signal microstrip path is low, and the inner layer signal radiation can also be shielded through the outer layer. From the point of view of EMI control, this is the best 4 - layer PCB structure available. The main note: two layers of signal and power mixed layer spacing to pull, walk the line perpendicular to the direction to avoid crosstalk; appropriate control board area, reflect the 20H rules; if you want to control the wire impedance, the scheme should be very careful to walk the floor with line layout in power and the bottom of copper island. In addition, copper deposits between the power supply or the formation shall be interconnected as possible as possible to ensure connectivity between the DC and the low frequency.

1.3, six ply laminates;

For the design of larger chip density and higher clock frequency, the design of 6 boards should be considered

Laminate mode:

1.3.1 SIGGNDSIGPWRGNDSIG;

In this program, the laminated scheme can achieve better signal integrity, signal layer and ground layer adjacent paired power layer and the ground layer, each layer can go line impedance controlled well, and the two layer are good energy absorption lines. And in the case of power and formation integrity, a better return path can be provided for each signal layer.

1.3.2 GNDSIGGNDPWRSIGGND;

In this program, the program applies only to the device density is not very high, the stack has all the advantages of the above layers, and that the top and bottom ground plane is complete, can be used as a good shield to use. It should be noted that the power layer is close to the surface of the non main component surface, because the underlying plane will be more complete. Therefore, the EMI performance is better than the first one.