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Power integrity design in PCB circuits
1 power integrity design is a very complex matter, but how to control the power supply system (power and ground plane) impedance is the key to design in recent years. Theoretically, the lower the impedance between the power supply system, the better the impedance, the lower the noise amplitude, the smaller the voltage loss. The actual design we can through the provision of voltage and power range maximum to determine the target impedance, we hope to achieve and then by factors related to the impedance adjusting circuit of each part of the power supply system (frequency dependent) to approximate the target impedance.
2) land bounce
When high speed devices edge rate is lower than 0.5ns, from the large capacity data bus data exchange rate is very fast, when it produces strong enough to affect the signal power in the corrugated layer, will produce power instability problems. When the current changes through the ground circuit, as the circuit inductance will produce a voltage, when the rising edge shrinks short, the current change rate increases, the ground bounce voltage increases. At this point, the ground plane (ground wire) is no longer the ideal zero level, and the power supply is not an ideal DC potential. When the gate circuit at the same time increases, the ground bounce becomes more severe. For a 128 bit bus, there may be 50_100 I/O lines switching over the same clock edge. At this time, the feedback of the power and ground loops of the I/O driver that is fed to the simultaneous switching must be as low as possible, otherwise a voltage brush will appear on the same ground. Ground bounce can be seen everywhere, such as chips, packages, connectors or circuit boards that may rebound, leading to power integrity problems. Need PCB to copy the board, you can contact us through the website to provide contact
From a technical point of view, the rising edge of the device will only decrease and the width of the bus will only increase. The only way to maintain ground bounce is to reduce the power and ground distribution inductance. For chips, it means moving to an array chip, placing power and ground as much as possible, and wiring to the package as short as possible to reduce inductance. For encapsulation, it means that the mobile layer is encapsulated so that the ground plane spacing of the power is closer, as in the BGA package. For connectors, it means using more ground pins or redesigning connectors to have an internal power and ground plane, such as a connector based ribbon cord. For the circuit board, it means to make the adjacent power and the ground plane as close as possible. As the inductance is proportional to the length, it is possible to minimize the ground noise by minimizing the power and ground connections.
3) decoupling capacitor
We all know that adding some capacitance between the power and the ground reduces the system noise, but how much capacitance does it add to the circuit board? How big is the capacitance of each capacitor? Where is each capacitor located better? We don't usually think about these problems seriously, just because of the experience of the designers, and sometimes we think that the less the capacitor, the better. In high-speed design, we must consider the parasitic capacitance, calculated out the number of decoupling capacitors and each capacitance and placed in a specific location, to ensure the system impedance in the control range, a basic principle of decoupling capacitors are needed, one less, the excess capacity a, don't.
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